1. Field of the Invention
The present invention generally relates to semiconductor chip manufacturing processes and more particularly to field effect transistor manufacturing processes that form devices with different operating voltages, but a single gate oxide thickness.
2. Background Description
Performance is a primary goal of logic design. Thus, to improve performance in field effect transistor (FET) integrated circuits (ICs) device features are constantly being shrunk. As device features shrink, FET gate insulator, i.e., gate oxide is being thinned and circuit/device operating voltages are being reduced, e.g., from 2.5 volts to 1.75 or 1.5 volts.
However, in some cases, state of the art IC chips are intended to be interfaced with otherwise incompatible, higher voltage IC chip families, e.g. 2.5 volts. These higher voltages increase the electric field across the devices' gate oxide such that these state of the art devices fail catastrophically, i.e., they are destroyed.
Further, a typical logic chip's input/output (I/O) circuit and the devices therein experience voltage overshoots and undershoots that require special decoupling. However, I/O circuits must accommodate these departures from normal operating voltages. Thus, even IC chips designed with a single gate oxide thickness and for a single operating voltage, for example, for 1.75 volts, have increased I/O circuit design complexity to accommodate these higher voltages. These I/O circuits could be simplified by increasing device gate oxide thickness, which would make the I/O circuits capable of handling the higher voltages. However, the increased oxide thickness comes, typically, at a price of degrading the rest of the chip's performance.
Consequently, efforts are made, constantly, to reduce the electric field across the gate oxide of FETs, both N-type FETs (NFETs) and P-type FETs (PFETs), without degrading the FET's performance. To that end, U.S. Pat. Nos. 5,471,081 and 5,523,603, both entitled "Semiconductor Device with Reduced Time-Dependent Dielectric Failures", both to Fishbein et al., U.S. Pat. No. 5,480,830 entitled "Method of Making Depleted Gate Transistor for High Voltage Operation" to Liao et al., and U.S. Pat. No. 5,637,903 entitled "Depleted Gate Transistor For High Voltage Operation" to Liao et al. (referred to herein collectively as "Fishbein and Liao") teach FETs made such that their gates remain depleted, increasing the effective thickness of the FET's gate oxide. This increased effective gate oxide thickness from the depleted gate provides some measure of increased operating voltage capability.
However, FETs as taught in Fishbein and Liao still suffer from high voltage gate to drain failures. When the drain of a Fishbein and Liao NFET is raised to, for example 2.5 volts (for a 1.75 volt process), with its gate at ground, the device's gate accumulates, nullifying the effect of the depleted gate, reducing the effective gate oxide thickness. Under these circumstances, the Fishbein and Liao device may break down at its drain.
Thus, there is a need for IC chips capable of tolerating a wider range of on-chip voltages, especially in chip input and output circuits, that do not impact circuit performance and design flexibility.